Mana Results
Home
GPA Calculator
Question Papers
JNTUK
JNTUH
JNTUA
Diploma APSBTET
Diploma TSSBTET
Savitribai Phule Pune University(To be Update soon)
Krishna University
Syllabus
Timetables
JNTUK Timetables
JNTUH Timetables
JNTUA Timetables
APSBTET Timetables
Login
Login
Contact
GATE
Previous Papers
POLYCET
EAMCET
ECET
LAWCET
ICET
UGC NET
Results
JNTUK Results
JNTUH Results
JNTUA Results
APSBTET Results
Branch
ADVANCED OPERATING SYSTEMS R05
ALGORITHMS FOR VLSI DESIGN AUTOMATION R05
MIXED SIGNAL LABORATORY R05
ADVANCED COMPUTER ARCHITECTURE R05
DSP PROCESSORS & ARCHITECTURES R05
CRYPTOGRAPHY AND NETWORK SECURITY R05
SYSTEM MODELING AND SIMULATION R05
HARDWARE SOFTWARE CO-DESIGN R05
SCRIPTING LANGUAGE FOR VLSI DESIGN AUTOMATION R05
LOW POWER VLSI DESIGN R05
DESIGN FOR TESTABILITY R05
Design for Testability R13
Semiconductor Memory Design & Testing R13
Low Power VLSI Design R13
VLSI Signal Processing R13
System on Chip Design R13
Digital Signal Processors & Architectures R13
CMOS Mixed Signal Circuit Design R13
VLSI LAB-II R13
Optimization Techniques in VLSI Design R13
Scripting Language R13
CAD for VLSI R13
CAD FOR VLSI ELECTIVEIII R16
SYSTEM ON CHIP DESIGN ELECTIVEIV R16
OPTIMIZATION TECHNIQUES IN VLSI DESIGN ELECTIVEIV R16
BACK END VLSI DESIGN LABORATORY R16
EMBEDDED SYSTEM DESIGN R16
CMOS MIXED SIGNAL CIRCUIT DESIGN R16
DESIGN FOR TESTABILITY R16
DSP PROCESSORS AND ARCHITECTURES ELECTIVEIII R16
LOW POWER VLSI DESIGN R16
VLSI SIGNAL PROCESSING ELECTIVEIII R16
SEMICONDUCTOR MEMORY DESIGN AND TESTING ELECTIVEIV R16